GPS-Disciplined Oscillator GPSDO Drives Electro-Mechanical (Analog) ClockCircuit converts unipolar GPSDO output to bipolar clock motor drive signal. A GPS-disciplined oscillator (GPSDO) provides precisely timed 100 mS unipolar (3.3V) pulses at one-second intervals (1 pps), synchronised to Coordinated Universal Time (UTC). A GPSDO can be had for around $100 from eBay. Figure 1 Figure 2 The input pulses from the GPSDO drive a CMOS CD4027 dual flip-flop (only one section is used). The flip-flop delivers a symmetrical 0.5 Hz square wave to the half-bridge driver circuit made of complementary (PNP/NPN) transistors. The output from the half-bridge is coupled to the clock motor through the 510Ω voltage dropping resistor and the 150 µF coupling capacitor. The circuit delivers alternating (positive/negative) 100 mS pulses to the clock motor. The circuit requires positive DC power in the range of 7-35 volts. It can be powered from the same source (wall wart) that powers the GPSDO. As BuiltClock Modification - Connecting to the Motor Winding
InitializationInitialization is done manually. Go to Official U.S. Time or other UTC source. With the clock running, move the minute and/or second hand as necessary until the clock displays the correct time. Do not force the hour hand. The clock will continue to tell the correct time to the second unless power is interrupted.
InstalledThe GPSDO is on the left. The converter/driver is in the white plastic box on the right.
Alternate Motor Driver
Circuit Accommodates Sweep-Style MovementMost bare quartz clock movements available today for repair or DIY are of the "sweep" persuasion. Rather than moving in one-second steps, the second hand moves continuously and steadily. This circuit converts the 1 pulse per second output from the GPSDO to a 16 PPS bipolar drive signal to spin the clock's two-pole motor at 8 revolutions per second (480 RPM). The movement's gear train reduces the 480 RPM motor speed to 1 RPM second hand speed. |
Figure 3
(sweep movement)
The heart of the circuit is a CD4046 CMOS phase-locked loop. The 16 Hz output from the 4046's voltage controlled oscillator (VCO) is divided by 16 through a couple of CMOS CD4027 dual JK flip-flops and fed back to the 4046 where it is phase-compared to the 1 Hz reference from the GPSDO. The voltage output from the phase comparator corrects the VCO frequency to precisely 16 Hz. The first CD4027 stage provides symmetrical 8 Hz (16 PPS) drive to the clock motor. The impedance of the motor winding is high enough so that it can be driven directly by the CMOS CD4027. back
As BuiltFollow the instructions above for clock modification. Initialization is the same as above except the sweep second hand should only be moved manually in the clockwise direction.
Addendum Other Available GPSDO OutputsA precise 10 MHz frequency reference output is also provided, useful for frequency calibration, along with a serial RS232 9600 BPS NMEA signal for use with GPS geolocation software. Neither of these outputs are used in the above clock applications but are always available.
Schematics produced with DCCAD.
Related LinksA GPSDO can be had for around $100 from eBay Futurlec (source for CMOS chips, resistors, etc.) Geolocation/Time Sync Software DE9 9 Pin Female to 3.5mm Male Plug Another GPSDO Application |