Early in the year 2012 WWVB began occasional on-air testing of a new binary phase-shift keyed (BPSK) time code transmitted simultaneously with the original amplitude-modulated code. The new code became a permanent part of the format in late 2012. See: Wikipedia - WWVB.

The new time data is encoded in 180-degree phase shifts of WWVB's 60 kHz carrier. Because of the shifting phase, my homebrew WWVB receiver was unable to lock to the carrier during periods when the biphase modulation was being tested, even though a very strong signal was being received. When the phase-shifted code became permanent the receiver would have been rendered permanently inoperative, unless...

It was obvious that for continued operation, the receiver would have to be redesigned or modified - changed in a fundamental way for the first time in 30 years. Modification was the easiest route: The circuit was changed by adding a frequency doubler - AD835N 4-quadrant multiplier chip - between the output of the RF amplifier stage and the phase detector circuitry. The receiver's carrier generator was also reprogrammed to double its frequency. The changes are shown below:

Circuit Before Modification

After Modification

Frequency Doubler (Squarer)

The AD835 could be thought of as an analog computer with two inputs. The chip multiplies the voltage at one input with the voltage on the other. By feeding identical signals to the two inputs the signal is "squared" (multiplied by itself). The result is that the input signal frequency is doubled. A sometimes useful side-effect of the squaring process is that a DC offset is acquired (a negative voltage squared becomes positive). In this case the DC offset is not desired. The output of the AD835 is AC-coupled to restore the signal baseline to zero volts (ground potential). The doubler circuit is shown below:

Figure 1

Frequency Doubler Circuit

Important Note: The circuit drawing (Fig 1) has changed slightly from the previously published version with the addition of a .1 µF cap and 10k resistor ahead of the AD835 multiplier chip. This restores the signal baseline to zero volts (ground potential). The change does not affect the circuit's function. If you would like to use the circuit in your application, please use this version.

[The less-expensive AD633 would probably work in this circuit, though the pinouts, biasing and power supply requirements are different. (May require an auxiliary power supply.) Consult the datasheet.]

Note: BAL (balance) is adjusted for best sinewave output symmetry (LF351, pin 6). If you do not have access to an oscilloscope, eliminate the 10k pot, 15k resistor .1 uF capacitor (*) and 2.7k resistor; ground pin 2.

After addition of the doubler circuit the 180° carrier phase shifts (now 360°) are virtually invisible to the receiver's phase detector. The conversion gain (Kφ) of the phase detector is increased somewhat (and thus system loop gain), but it doesn't seem to affect the operation of the overall system much. The receiver now goes a little berserk at the ±45° shifts at minutes 10 and 15, but settles quickly. [It appears the ±45° shift is not included when the BPSK code is being transmitted. Good!] Otherwise the receiver now chugs along as before. [WWVB has tweaked the phase reversals since early testing so as to make the BPSK code even less apparent to the modified receiver.] Decoding of the amplitude-modulated original time data also resumed after the modification. [I have no plans to add biphase time code recovery capability to the receiver, though it would be an interesting exercise.] The modified receiver will continue to be useful as a frequency standard, as it has for the last 30 years.

Photo

Note 1970's technology / homebrew construction.

Addendum 1: Receiver Front-End

In response to a couple of queries from readers about the WWVB receiver's RF amplifier and AGC circuit, I've decided to include a schematic of that circuit here in case someone else is interested. Because all of the original documentation has been lost, I had to back-engineer the thing a little in order obtain enough information to allow installation of the frequency doubler circuit described above. The RF amplifier/AGC circuit appears below.

Figure 2

RF Amplifier

Current-controlled amplifier - U3 & U4

The key to the circuit's operation is U3, a CA3080 transconductance amplifier. Combined with U4, LM6171 opamp, the pair provides something like -20 to +60 dB of variable (current-controlled) gain. U3 is not a voltage amplifier; it must be combined with the LM6171 (or similar fairly high-speed opamp) to provide voltage gain. The gain of the pair is controlled by U5, the AGC amplifier. A more-positive output from the AGC amp drives more current into pin 5 of the CA3080, generating more gain in the CA3080/LM6171 pair. The circuit originally had an LM318 in the U4 spot. The LM6171 is less fussy than the 318.

The tuned input circuit (6.8mH inductor, 001µF capacitor), along with a similar circuit in the active antenna, provides only modest selectivity at 60 kHz. The receiver's extremely narrow bandwidth (<1Hz) is provided by the loop filter downstream.

AGC amplifier - U5

The two 1N34 diodes, along with the .1 uF capacitors and 100k resistor, form an envelope detector. The rectified input signal voltage appears on C1. This voltage is amplified by U5, the output of which controls the gain of U3 through the 47k resistor. The response time of the AGC amplifier is very slow - the circuit acts as an averaging detector, even with WWVB's very slow modulation. That long time constant makes the AGC circuit (almost) impervious to short noise spikes.

Addendum 2: And the Rest of the Receiver??

Unfortunately, back-engineering the front end did not include the balance of the receiver downstream from the RF amplifier/frequency doubler. The general layout is shown below.

Phase Detector/Loop Filter/VCXO/Carrier Generator

The phase detector in the receiver is a sampling type and operates in linear mode - unsaturated. That type detector, combined with the AGC-controlled front end, is less susceptible to random noise and signal amplitude variations. As the input signal gets noisier, ie, the signal amplitude decreases relative to noise, the detector's conversion gain goes down and loop bandwidth automatically narrows.

The shots below show the operation of the phase detector. The system is locked to the incoming signal as shown.

Phase Detector In	Phase Detector Out

The detector converts the phase of the incoming signal - relative to the locally-generated carrier - to a voltage.

I don't remember specifics on the loop filter, except that I used Howard M. Berlin's Design of Phase-Locked Loops with Experiments (H.W. Sams, 1978) as a design guide. The filter is a damped low-pass type - strictly analog, consisting of resistors, capacitors and an opamp or two. It's a "two-speed" affair. It comes up in 'wide' mode for quick lock, then switches to narrow when lock is achieved. At such time as loss of lock is detected, it switches back to wide. [The loss of lock situation will occur when WWVB occasionally goes off air.] The loss-of-lock indication, OR'd with a complimentary loss-of-signal indication from the receiver's synchronous amplitude detector (part of the time-code recovery part of the receiver), lights an indicator LED on the front panel and issues a TTL-level "loss-of-carrier" signal through a connector on the rear panel.

The DC output of the loop filter is compared to zero reference (ground) and the difference voltage is highly amplified. The loop filter/amplifier output voltage varies the frequency of VCXO. The system operates isochronously: The frequency of the VCXO/carrier generator is driven by the loop amplifier so as to produce zero net volts on the sampling capacitor at the output of the phase detector (zero net phase error).

The VCXO is a simple TTL-based crystal oscillator (from Poly Paks - anybody remember Poly Paks?) with a varactor diode added across one of the frequency trimming capacitors. That thing has exhibited remarkably little long term drift over the years - I may have re-adjusted it twice in 30 years. It does exhibit some variation due to changes in ambient temperature, but being in a disciplined environment (in the loop), it matters little.

The carrier generator is made up with CMOS counters and CD4046 phase-locked loop ICs, the exact details of which have faded from memory. Back engineering that part of the receiver would require a major tear-down and, barring a failure which would require going in to affect repairs, probably won't happen.

The receiver also has the capability to recover WWVB's amplitude-shifted time code. The time code is used by millions of radio-controlled clocks around North America to stay synchronized. The time (UTC or local) is displayed on the front panel. [Since a radio-controlled clock can be had relatively cheaply nowadays, this function has been rendered redundant, though I would like to think this receiver, with its synchronous AM detector, would out-perform the el-cheapos in difficult situations.]

Synchronous AM Detector

The front panel also includes lots of other lights, switches and meters (phase error, correction voltage, AGC), including a display of the shift register that receives the time code. For a photo click one of the links below.

From Comments/Questions

Schematics produced with DCCAD.